A tradition flash memory may comprise silicon-oxide-nitride-oxide-silicon (SONOS) cells having a two-transistor (2T) structure that prevents over-erase and drain voltage disturb. However, during programming, the cell's channel has to sustain a 5V punch-through voltage and therefore the channel length of the conventional 2T SONOS cell cannot be scaled down below a set limit. For example, the 2T SONOS cell may be programmed using Channel-Hot-Hole-Induced-Hot-Electron (CHHIHE) injection. During this type of programming, the drain to source voltage (VDS) of the cells is typically set to five volts to produce high channel current. Typically, a large charge-pump circuit is utilized to produce this high channel current. This increases the die size and cost and is particularly not suitable for lower density applications. The high VDS requirement also significantly limits the scalability of the cell's channel length and therefore the overall array size.
The 2T SONOS cells may also be programmed using Band-To-Band-Tunneling (BTBT) injection. During this type of programming, the cell's VDS is also 5V. Again, the high VDS requirement significantly limits the scalability of the cell's channel length. Thus, the overall size of conventional flash memory is determined by the size of any required charge-pump circuitry and the scalability of the 2T SONOS cells. As a result, the overall size cannot be reduced below that which is necessary to support the required channel length of the cells.
It is therefore desirable to have a flash memory that utilizes two transistor memory cells and that overcomes the problems of scalability associated with conventional flash memories.